1. Technical Field
The disclosed technology relates to a semiconductor memory device and a power initializing method thereof and, more particularly, to a semiconductor memory device based on wireless signal transmission between chips, which is capable of optimizing signal transmission power, and a power initializing method thereof.
2. Description of the Related Art
The capacity and operating speed of a semiconductor memory device used as a memory in most electronic systems are increasing due to continued development in the semiconductor industry and in response to user requests. Furthermore, various attempts to mount a memory with larger capacity in a smaller area and drive the memory at a higher speed are being made. To mount a large-capacity memory in a small area, a plurality of semiconductor chips can be stacked in a single semiconductor package. FIG. 1 illustrates various structures for providing signals to a plurality of semiconductor chips included in a semiconductor package.
Referring to FIG. 1, the semiconductor package includes a substrate 1 and multiple semiconductor chips 2A and 2B. The semiconductor chips are stacked on one side of the substrate 1, and the substrate 1 provides a signal supplied from an external controller (not shown) to the semiconductor chips. The semiconductor chip 2A can be a chip including a logic circuit for operating a memory chip and the semiconductor chip 2B can be a memory chip including a memory cell array that receives a signal provided by the semiconductor chip 2A and operates according to the received signal.
FIG. 1A illustrates a structure in which a signal is provided to the semiconductor chips 2A and 2B through wire bonding, and FIG. 1B illustrates a structure in which a signal is provided to the semiconductor chips 2A and 2B through a via. Although the wire bonding structure illustrated in FIG. 1A is a low manufacturing cost arrangement, the number of wires connected to the semiconductor chips 2A and 2B is limited and signal transmission paths are long. The signal transmission structure using a via as illustrated in FIG. 1B is advantageous in terms of the number of vias and a signal transmission path. However, the signal transmission structure using a via is a high manufacturing cost arrangement and causes the deterioration of yield in order to secure a known good die (KGD).
FIG. 1C illustrates a structure that includes wireless signal transmission between the semiconductor chips 2A and 2B. When the semiconductor chip 2A including a logic circuit provides a signal to the semiconductor chips 2B including memory cells, the signal can be transmitted according to a capacitive coupling or inductive coupling method, in which case a signal can be transmitted to at least three semiconductor chips. This wireless signal transmission between semiconductor chips does not require an additional process for connecting a wire or forming a via. In addition, the wireless signal transmission between semiconductor chips allows for easy addition or subtraction of chips to increase yield in terms of KGD and to improve the density of channels for signal transmission.
In the case of a semiconductor memory package including a plurality of semiconductor chips in a stack structure, if signals having the same power are provided to signal-receiving semiconductor chips even though the semiconductor chips have different signal communication distances, an error may be generated in the signals provided to the signal-receiving semiconductor chips. When a signal is wirelessly transmitted between semiconductor chips, as illustrated in the structure of FIG. 1C, the transmission power of the signal provided to each of the semiconductor chips must be appropriately controlled so that an error is not generated in the signal provided to the semiconductor chips.
FIG. 2A illustrates a conventional circuit for setting signal transmission power, and FIG. 2B illustrates a signal power test result according to a signal communication distance and signal transmission power. Referring to FIG. 2A, a means 10 for controlling the transmission power of a signal can include a control register 11 and four power controllers 12a, 12b, 12c and 12d. A result obtained by accessing the control register 11 is provided to each of the power controllers 12a, 12b, 12c and 12d, and a current It having a magnitude according to the width W of a predetermined transistor included in each of the power controllers 12a, 12b, 12c and 12d is generated. The current It is controlled according to the access result, the power of the signal is controlled according to the current It, and the signal with the controlled power is provided to a semiconductor chip.
Referring to FIG. 2B, when a signal is provided to a semiconductor chip having a short communication distance, the signal transmission is checked as “pass” even though the signal is provided to the semiconductor chip with low transmission power. However, the signal should be provided to a semiconductor chip having a long communication distance with high transmission power. The power of the signal when the test result corresponds to “pass” is measured to set the control register 11.
However, this signal transmission power setting method requires a long time to set the control register. Furthermore, when signal transmission fails due to a variation in the surrounding environment after the control register is set, the transmission power needs to be reset.